TSMC Completes Design of 5nm EUV Process Node

Discussion in 'Hardware Components and Aftermarket Upgrades' started by hmscott, Apr 6, 2019.

  1. hmscott

    hmscott Notebook Nobel Laureate

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    TSMC Completes Design of 5nm EUV Process Node
    by Lucian Armasu April 5, 2019 at 8:20 AM - Source: TSMC
    https://www.tomshardware.com/news/tsmc-5nm-euv-process-node,38995.html

    TSMC and OIP Ecosystem Partners Deliver Industry’s First Complete Design Infrastructure for 5nm Process Technology

    Enabling next-generation silicon designs targeting advanced mobile and high-performance computing applications
    Issued by: TSMC Issued on: 2019/04/03
    https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=THPGWQTHTH&language=E
    https://www.tsmc.com/uploadfile/pr/newspdf/THPGWQTHTH/NEWS_FILE_EN.pdf

    TSMC initiates risk production for its 5 nm node, reveals performance details
    by Bogdan Solca, 2019/04/05
    https://www.notebookcheck.net/TSMC-...ode-reveals-performance-details.415837.0.html

    "Initially scheduled for mid-2019, risk production for the upcoming 5 nm manufacturing process was already initiated at the end of March.

    TSMC also finalized the 5 nm design infrastructure and it is currently testing this process through multiple silicon test vehicles.

    Improvements over the current 7 nm process include 1.8X increased logic density and a 15% performance boost."

    TSMC 5nm Risk Production Starts; Process Delivers 15% Performance Gain
    By Ramish Zafar, Apr 4
    https://wccftech.com/tsmc-5nm-production-euv/

    "Except for Intel, foundries all over the world are moving fast with next-generation lithography and manufacturing processes. While the Santa Clara chip giant has a clear transistor density advantage over others, marketing departments often ‘forget’ this fact, and continue to portray things direr than they really are. Now, TSMC has commenced risk production for 5nm and validated the process design with its OIP (Open Innovation Platform) partners. Take a look below for more details: (see site)

    TSMC’s 5nm Process Delivers 1.8X Logic Density And 15% Performance Gain When Compared To 7nm"
     
    Last edited: Apr 6, 2019
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  2. hmscott

    hmscott Notebook Nobel Laureate

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    TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready
    by Anton Shilov on April 5, 2019 12:00 PM EST
    https://www.anandtech.com/show/1417...pdk-drm-eda-tools-3rd-party-ip-ready#comments

    "TSMC this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

    TSMC’s N5 is the company’s 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).
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    TSMC finished development of N5 some time ago and its alpha customers with access to pre-production tools are already risk producing chips using the technology. Meanwhile, TSMC has finalized its 5 nm design rule manual (DRM), process design kits (PDKs), and SPICE (simulation program with integrated circuit emphasis) model for those clients who prefer to work with a stable version of design infrastructure.

    Besides TSMC’s tools, chip developers can also use a comprehensive set of EDA (electronic design automation) tools from ANSYS, Cadence, Mentor Graphics, and Synopsys. TSMC says that EDA programs from the said companies fully support N5 DRM to ensure necessary accuracy, routability for optimized power, and other aspects of the technology. Obviously, all the tools have been certified by the contract maker of semiconductors.

    Finally, TSMC and its partners have also developeda comprehensive N5 IP portfolio that is currently focused primarily on HPC and mobile SoCs. TSMC’s Foundation IP includes high-density and high-performance sets of standard cell libraries and memory compilers. Meanwhile, the company’s partners offer a variety of IP cores for N5 SoCs, including DDR, LPDDR, MIPI, PCIe, and USB PHYs.

    “TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

    All the tools required for development of chips to be made using N5 fabrication technology are available from TSMC and its partners right now."
     
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  3. jaybee83

    jaybee83 Biotech-Doc

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    juuuust to make sure everyone sees this :rolleyes: most people tend to forget that those "x nm" designations are just marketing mumbo jumbo and don't reflect the actual transistor density / area & power requirements / performance of a specific arch design :p
     
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  4. hmscott

    hmscott Notebook Nobel Laureate

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    How about we wait for Intel Kudo's on claimed superiority until Intel actually ship something we can buy and use in the desktop 1151 / 2066 socket or follow-on desktop realm? The ULV 10nm finger food, minus IGP, doesn't count.

    Mumbo jumbo is all Intel has been feeding us about 10nm for 7 years and more, FAB 42. More... FAB 42 7nm... FAB 28...

    "The 14nm fabrication node will start as soon as 2013, while the 10nm process is expected in 2015 and both the 14 nm and 10 nm processes will feature the Tri-Gate 3D transistor design which allows for more energy efficient processors to be built. 2015 will mark the introduction of the company’s 10nm fabrication technology, that is also known internally under the “P1274” process name."

    Intel has slung and re-slung enough 10nm BS to cause us to all begin to doubt Intel will ever deliver on 10nm as originally promised.

    Intel licensing 7nm from somewhere outside to get back in production with competitive product wouldn't be a surprise to me.
     
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  5. jaybee83

    jaybee83 Biotech-Doc

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    oh, naturally! don't get me wrong, i wasn't defending Intel or claiming they will offer superior products this year compared to AMD or others. just saying that going by the "x nm" alone will not get you anywhere :)

    i could imagine intel's "10 nm" process to be comparable to other "7 nm" designs in transistor density.
     
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  6. Vasudev

    Vasudev Notebook Nobel Laureate

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    I think Samsung will be providing the 10nm and 7nm nodes because Intel GPUs can save costs by ordering the nodes, memory chips (VRAM,ROMs etc). 14nm is nearly dead because now everybody needs more power rather than rely on pure single threaded benchmarks/worloads, they tweak multi-core clocks or even multi-CPU/socket/hybrid versions to get the job done quickly.
    People rarely look at datasheets. Intel should move to 7nm this quarter otherwise their investors will pull out. So, no money for R&D and still chips will use 14nm++++---++++........ ∞
     
    Last edited: Apr 6, 2019
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