TSMC Completes Design of 5nm EUV Process Node by Lucian Armasu April 5, 2019 at 8:20 AM - Source: TSMC https://www.tomshardware.com/news/tsmc-5nm-euv-process-node,38995.html TSMC and OIP Ecosystem Partners Deliver Industry’s First Complete Design Infrastructure for 5nm Process Technology Enabling next-generation silicon designs targeting advanced mobile and high-performance computing applications Issued by: TSMC Issued on: 2019/04/03 https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=THPGWQTHTH&language=E https://www.tsmc.com/uploadfile/pr/newspdf/THPGWQTHTH/NEWS_FILE_EN.pdf TSMC initiates risk production for its 5 nm node, reveals performance details by Bogdan Solca, 2019/04/05 https://www.notebookcheck.net/TSMC-...ode-reveals-performance-details.415837.0.html "Initially scheduled for mid-2019, risk production for the upcoming 5 nm manufacturing process was already initiated at the end of March. TSMC also finalized the 5 nm design infrastructure and it is currently testing this process through multiple silicon test vehicles. Improvements over the current 7 nm process include 1.8X increased logic density and a 15% performance boost." TSMC 5nm Risk Production Starts; Process Delivers 15% Performance Gain By Ramish Zafar, Apr 4 https://wccftech.com/tsmc-5nm-production-euv/ "Except for Intel, foundries all over the world are moving fast with next-generation lithography and manufacturing processes. While the Santa Clara chip giant has a clear transistor density advantage over others, marketing departments often ‘forget’ this fact, and continue to portray things direr than they really are. Now, TSMC has commenced risk production for 5nm and validated the process design with its OIP (Open Innovation Platform) partners. Take a look below for more details: (see site) TSMC’s 5nm Process Delivers 1.8X Logic Density And 15% Performance Gain When Compared To 7nm"