The ThrottleStop Guide

I already mentioned that a while ago it fluctuates the cache speed less than 1 seconds and comes back I realized it by coincidence when I was adjusting the ICCMAX sometimes TS doesn't catch it due to very fast cache speed switching so.. I confirmed it using HWInfo

Edited:-
Here with HDC enabled by just simply switching it to [Enable] Through Power Plan


With HDC Disabled

 

Not sure what i am doing wrong but current on my Mi Air 13.3 laptop with the i5 8250U, i tried using Throttlestop to offset voltage for the cpu core via FIVR. But every offset i do does not show up on the chart on the top right portion.

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edit, ok.. found the problem.. the device has been locked in the bios to prevent undervolting.. oh well.. looks like i am out of options

edit2, after following the guide at https://forum.xda-developers.com/showpost.php?p=77626628&postcount=11 i've managed to unlock my device for undervolting... yay

 

Does anyone know if the i9 8950hk can reach deeper c states than c3? at least on the alienware 17

 

Yes it can go as deep as C10 but the problem is not here... the problem is... it depends on OEM & BIOS if they allowed you to reach to those deep states or not

 

Knowing dell with alienware probably not then

 

Alright guys... Here is it to have the option to change the scheme for Intel DPTF Power Modes after testing all three modes [Low,Medium,High Performance] I didn't see a significant difference on battery life or heat differences so... anyway.. it is here for anyone who want to try it out and let us know if you see any kind of differences

If the first one didn't work.. try the second one.. but always be sure that you have DPTF enabled on your BIOS as without it.. it won't work even if it appears on the power plan it will still won't work

Example to what I see from the Power Plan...


Enjoy if it works out for you

 

It will be a sad day when all manufacturers disable undervolting in their laptops.

If you have the time, can you try toggling HDC on and off by using RWEverything? I would like to add a check box like this to TS so users can toggle HDC. Installing the DPTF driver is not for everyone.

 

HDC Disabled
Stuff open
https://i.postimg.cc/vm5wQ6tZ/screenshot.png 5.1W
Desktop only
https://i.postimg.cc/pdf3NMP9/screenshot.png 3.7W

HDC Enabled via PKG_HDC_CTL MSR
Stuff open
https://i.postimg.cc/90nnPWYk/screenshot.png 5.1W
Desktop only
no screenshot - but package power is still 3.7W

HDC makes no difference for me

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For those wondering what the hell is going on

Per the intel documentation (page 17):
Hardware duty cycling (HDC) enables the processor to autonomously force a logical processor, processor core, or physical package to enter an idle state (to C3 or deeper). HDC forced idle operation can be thought of as operating at a lower effective frequency. The effective average frequency computed by software will include the impact of HDC forced idle. The primary use of HDC is to enable system software to manage low active workloads to increase the package level C6 residency. HDC is disabled by default on processors that support it.

Here is what these registers do:

Code:

HDC "BASELINE AVAILABILITY RESOURCE"

CPUID.06H:EAX.[13]=1 means that If you execute CPUID instruction with register EAX = 06H (6 in hexadecimal) as input, you will get the result in EAX. If the bit number 13 of the result is 1, the bit is enabled. In this case, when bit number 13 is enabled the CPU HDC performance counters will be enabled: THREAD_STALL, CORE_HDC_RESIDENCY, HDC_SHALLOW_RESIDENCY, HDC_DEEP_RESIDENCY. The Package and logical-processor level HDC control MSRs (IA32_PKG_HDC_CTL_MSR, IA32_PM_CTL1) are also only writable if bit number 13 is 1.

-----------------------------------------------
HDC PROGRAMMING MSRs

PKG_HDC_CTL (bits 1:0) enables HDC operation by allowing the processor to force-idle all "HDC Allowed" logical processors.
This bit defaults to 0 (HDC disabled) for all logical processors.
This bit is only writable if CPUID.06H:EAX[bit 13] = 1

PM_CTL1 (bits 1:0) allows each logical processor to honor the PKG_HDC_CTL setting. 
This bit defaults to 1 (HDC allowed) for all logical processors.
This bit is only writable if CPUID.06H:EAX[bit 13] = 1

-----------------------------------------------
HDC RESIDENCY COUNTERS
(IA32_THREAD_STALL_MSR, MSR_CORE_HDC_RESIDENCY, MSR_PKG_HDC_SHALLOW_RESIDENCY, MSR_PKG_HDC_DEEP_RESIDENCY)
(Accessing all except THREAD_STALL_MSR will cause #GP fault unless CPUID.06H:EAX[bit 13] = 1 )

THREAD_STALL (bits 63:0) will report HDC forced idle count (stalled cycles) since last RESET.
This counter increments at same rate as TSC counter, and only updates after the logical processor exits its forced-idle-C state.
It also indicates the forced-idle cycles due to HDC that could appear as C0 time to traditional OS accounting mechanisms.
This counter is available only if CPUID.06H:EAX[bit 13] = 1.

CORE_HDC_RESIDENCY (bits 63:0) tracks per-core HDC residency when the core is in C3 or deeper (when all logical processors of this core are idle due to HDC or other mechanisms) and at least one of the logical processors of the core is in a HDC forced idle state.
This counter increments at same rate as TSC counter, and only updates after the logical processor exits its forced-idle-C state.
If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR will cause a #GP fault.

HDC_SHALLOW_RESIDENCY (bits 63:0) tracks HDC residency time when the package is in C2 state, all cores in the package are not active and at least one logical processor was forced by HDC into idle state.
This counter increments at same rate as TSC counter, and only updates after the logical processor exits its forced-idle-C state.
This counter may be implementation specific.
If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR will cause a #GP fault.

HDC_DEEP_RESIDENCY (bits 63:0) tracks HDC residency time when the package is in a software-specified package Cx state. The Cx state monitored is stored in last bits 2:0 of MSR_PKG_HDC_CONFIG (0: no-counting [default]; 1: count package C2 only, 2: count package C3 and deeper; 3: count package C6 and deeper; 4: count package C7 and deeper. [CPUID.06H:EAX[bit 13] must be 1])
This counter increments at same rate as TSC counter, and only updates after the logical processor exits its forced-idle-C state.
If CPUID.06H:EAX[bit 13] = 0, attempt to access this MSR will cause a #GP fault.

I think CPUID.06H:EAX[bit 13] is set to 1 for me. So not sure why HDC isn't doing anything for me.
(CPUID 0x00000006 [ 0x000027F7 0x00000002 0x00000009 0x00000000 ])

 

Roger that..

Here with editing the MSR to disable HDC & showing TS the power consumption became higher immediately


And this with editing the MSR to enable HDC and showing TS the power consumption went lower immediately


I edited the MSR using CrystalCPUID from here https://crystalmark.info/software/CrystalCPUID/index-e.html
I hope it helps

Have you checked your BIOS have DPTF enabled? because I think(not sure) HDC is one of the features of DPTF so... DPTF is the main function in order to enjoy other kind of features like LPM ,HDC ,Power Limit ,Acoustics Limit , etc...

 

No difference for me either.

Keep in mind that power consumption is not measured power consumption. It is some sort of approximation and when a CPU is idle, it is far from 100% accurate. A much more accurate number is the package temperature. In your original screenshots, there was no change. In your second set of screenshots, the package temperature actually went up a couple of degrees even though the power consumption number went down. That does not make sense so I am still skeptical if enabling HDC is accomplishing anything or not.