The ThrottleStop Guide

Discussion in 'Hardware Components and Aftermarket Upgrades' started by unclewebb, Nov 7, 2010.

  1. T1mur

    T1mur Notebook Guru

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    Hm, I forgot to stop Cstate and kept it running and guess what, "accidentally" I just glimpsed some C3 readings.

    But with most profiles these only happen for a brief moment right when increased CPU load happens. Like maximizing Firefox or starting a torture test in Prime (or load test in Ableton Live). Then all falls back to 0.0 again.

    Performance Monitor on the other hand reports 99.xy% C3 with the idle "Balance" power-profile. Maybe these are all C7?

    Interestingly one of my customized profile that Performance Monitor reports nearly 50% C2 (and no C3) at idle makes Cstate report around 10-45% C3 (mostly around 20. Still no C6 reported with any profile.

    PS: In this profile TS' Power Saver decreases idle wattage from around 87w to 68-73w. No difference though when C1E is enabled. Anyway this specific profile is meant to keep Core Parking and C1E disabled (see how all cores run at fixed +1 Turbo bin even at idle). So Power Saver can be a very useful option when specifically pushing CPU limits.
     

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  2. unclewebb

    unclewebb ThrottleStop Author

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    The CState program doesn't use any ACPI functions. Core i CPUs have two C State counters for each core. When a core is in the C3 state, the CORE_C3_RESIDENCY counter at MSR 0x3FC increments upward. When a core is in the C6 state, the CORE_C6_RESIDENCY counter at MSR 0x3FD also counts upward. It's very simple for software to read these counters every second and determine what percentage of time that CPU core was in C3 or C6. Both of these registers are read only so the OS or any other software should not be able to interfere with getting reliable data from these counters.

    I know the CState program is reading these correctly so I'm having a hard time trying to explain your first screen shot. If the CPU Package is spending time in C6 than all of the individual cores must also be spending time in C6 so your first screen shot that shows a row of 0.0 doesn't add up.

    After digging through the Intel docs I found that it is possible for an operating system to block software access to the time stamp counter (TSC) within a CPU. Windows doesn't do this so I've always ignored this possibility but Apple might be blocking this. There is a method I can use to try and work around this and you can see if it makes any difference to your results. If your results are the same then I guess you can't trust the CState program.

    I also found this in the November 2008 Intel Turbo Boost docs.

    So when a CPU is in the C3 or in the C6 sleep state, Windows could report this as either ACPI C2 or ACPI C3 depending on the BIOS.
     
  3. unclewebb

    unclewebb ThrottleStop Author

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  4. Jas71

    Jas71 Notebook Evangelist

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    I'm sure you have already answered this, but there isn't much I can do to increase performance on my 2720qm right?
     
  5. T1mur

    T1mur Notebook Guru

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    Same picture with 1.1, sorry. What confuses me is that Cstate reports Windows C2 as C3, but the percentages are very different for most cores.

    Btw, that was the second Intel white paper I (already) read when our discussion became more complex. ;) Notice how it says "is considered an inactive Core" for Turbo Boost. That does not mean it has to be parked Though I am not sure what exactly defines "parking" yet.
     
  6. unclewebb

    unclewebb ThrottleStop Author

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    Jas71: I think the M17x-R3 bios blocks most ThrottleStop adjustments so you can't do anything with a 2720QM.

    T1mur: I didn't have very high hopes that CState 1.1 would solve the reporting issue you have on your Apple. As the Intel docs I posted above show, it's impossible to know what Windows will report for ACPI C2 or ACPI C3. For comparison, you could ask another user to do some testing on a PC but the PC bios could decide to report CPU C3/C6 completely differently than what your Apple bios does.

    Core parking is still a mystery to me too and I don't know what the official definition of a parked core is either. From the testing I've seen, no thread spends 100% of the time parked in an inactive state. They are always being woken up, multiple times per second, to take care of some background processing.

    At idle if you are curious about your C3 and C6 Core CState counters you could try reading these directly with my MSR Tool. It lets you read registers directly from the CPU.

    http://www.mediafire.com/?myjkxzkzzmd

    When you run it, enter 0x3FC in the MSR Number box at the bottom and then push the Read MSR button multiple times to see if this is increasing. This will let you look at the C3 Residency counter and you can look at MSR 0x3FD to keep an eye on the C6 Residency counter.

    You should also be able to read the Time Stamp Counter by looking at MSR 0x10. If you keep clicking on the Read MSR button, you should always see this register increasing. The only time it is supposed to get reset is when you reboot. I'm glad I don't have your computer for a day or I might go nuts trying to figure it out.
     
  7. T1mur

    T1mur Notebook Guru

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    I will give Cstate a try on the i3 of my wife's Acer laptop.

    0x3FC keeps counting up when I use the profile hat also makes Windows C2 and Cstate count percentage (though they are still in disagreement over the value).

    0x3FD stays at 0 (zero) for all cores EDX + EAX

    0x10 keeps counting up fast
     
  8. T1mur

    T1mur Notebook Guru

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  9. T1mur

    T1mur Notebook Guru

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    I noticed that MSR 0x3FE keeps counting up depending on CPU load and power-profile and seems to be a core C7 counter according to the following list:

    Code:
    #define MSR_TSC	0x10
    #define MSR_NEHALEM_PLATFORM_INFO	0xCE
    #define MSR_NEHALEM_TURBO_RATIO_LIMIT	0x1AD
    #define MSR_APERF	0xE8
    #define MSR_MPERF	0xE7
    #define MSR_PKG_C2_RESIDENCY	0x60D	/* SNB only */
    #define MSR_PKG_C3_RESIDENCY	0x3F8
    #define MSR_PKG_C6_RESIDENCY	0x3F9
    #define MSR_PKG_C7_RESIDENCY	0x3FA	/* SNB only */
    #define MSR_CORE_C3_RESIDENCY	0x3FC
    #define MSR_CORE_C6_RESIDENCY	0x3FD
    #define MSR_CORE_C7_RESIDENCY	0x3FE	/* SNB only */
    http://ftp.kernel.org/pub/linux/kernel/people/lenb/acpi/utils/pmtools/turbostat/turbostat.c

    "SNB only" should mean Sandy Bridge only. The other MSR return values for me, too (package C7 and C2).

    Thanks for pointing me to "MSR", this allowed me to find that "Turbostat" utility. I will try to run/compile Turbostat on OS X. Would finally give me some insight on how OS X CPU kext handles these things (and why some audio applications are so badly affected while others are not).
     
  10. unclewebb

    unclewebb ThrottleStop Author

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    The TSC (Time Stamp Counter) counts up at the default frequency of the CPU so it will always be counting up very quickly. To work out most of these ratios, you compare these other counters to the TSC and work out a percentage.

    RealTemp and ThrottleStop can report reasonably accurate temperatures from a wide variety of Intel Core 2 and Core i CPUs but ultimately, all temperature monitoring programs are limited by the quality of sensors that Intel uses as well as the lack of accurate engineering data that Intel has publicly released about these sensors. The 45nm Core 2 temperature sensors are horrible but most of Intel's other sensors they have used are pretty good.

    With the newer Core i CPUs, Intel started including a value for TJ Target within a register in the CPU. Before they did this, monitoring software had to guess at this value. This was a big improvement but there is still the problem that actual TJMax can be different than the TJ Target value so 100% accurate temperatures from idle to TJMax are not possible.

    RealTemp chose to ignore the invalid data bit in the CPU for a reason. Ignoring this bit provided a way to report reasonably accurate temperatures between 100C and 130C. Intel used an Engineering Sample ES processor with broken sensors and showed why this is not always such a good idea but completely defective temperature sensors on retail CPUs is very rare.

    During my testing, I found that the DTS data would wrap around like an old speedometer. At DTS 0, the core temperature was 100C. If the CPU got hotter the DTS data would wrap around and start counting down again so DTS 127 = 101C, DTS 126 = 102C, etc. and this would keep right on going up to the thermal shutdown temperature at 125C to 130C. I tested that once or twice. :D

    I don't think Intel was too impressed by my discovery. When the Core i7 was introduced, Intel blocked this so the data coming from these sensors no longer wraps around. As the CPU gets hotter and hotter beyond the thermal throttling point, the Core i DTS sensor just keeps putting out a value of zero.

    If you have any specific questions, just ask.

    Your table of MSR values is correct according to Volume 3B of the Intel docs and SNB must stand for Sandy Bridge.

    I'll consider creating a one off version of ThrottleStop so you can monitor C2 and C7 package state instead of C3 and C6. It might show what your CPU is doing when idle.
     
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