SoftFSB OCing 4 Linux (Dev)

Discussion in 'Linux Compatibility and Software' started by Darth_nVader, Oct 30, 2009.

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  1. Darth_nVader

    Darth_nVader Notebook Consultant

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    If we look at lfsb, it has code for SMBus 2.0, but needs i2c-dev-> needs and SMBus driver like i2c_i801->they both need the linux kernel.

    I don't think that it is reasonable or wise to try to gain access to the SMBus in a BootLoader, sure it can be done, however you turn your bootloader into a mini OS.

    However, if you enumerate your SMBus as an ACPI device in the DSDT of your bios, you can then use ACPI code to R/W to your SMBus, but I believe this may limit to one off code for each Logic Board.

    If we look past x86 Bios, EFI or OpenFirmware, these are Modular Mini OSes, that can Load and execute code from the HD, and with EFI it's C.

    So, it's not really practical to try with GRUB, but could be done via ACPI and GRUB, I'm just not sure each Logic Board would not need it's own code.
     
  2. Darth_nVader

    Darth_nVader Notebook Consultant

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    Ok, thanks Nando4, that works for me as well.

    I made a few changes to your ics9lprs355.c, as my RTM875t-606 needs a few tweaks, I need to make it's own rtmxxx.c, but it's working just fine.

    I'm running a Bootloader for *BSD that has some features Grub does not offer, so I'm Chainloading from Grub like so:

    Code:
    root (hd1)
    chainloader +1
    HD1 is the Disk and I don't offer it a Partition, so it just reads to MBR and loads my other Bootloader.

    Also, for whatever reason, Grub can't seem to find setfsb.mod unless I give the Full $PATH, so if anyone runs into that:

    Code:
    insmod (hd0,1)/boot/grub/setfsb.mod
    Where (hd0,1) is the disk and partition that /boot/grub/setfsb.mod is on.

    You can:

    Code:
    ls (hd0,1)/boot/grub/
    To make sure you have the correct disk and partition.
    :D
     
  3. Darth_nVader

    Darth_nVader Notebook Consultant

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    Nando4, here is what the RTM875t-606.c looks like, NOTE: It will compile and run, However, setpll ics9lprs355, so some edits still need to be made and merged.

    Code:
    /*
    *  C Implementation: RTM875T-606
    *  Note: This file still needs to be Edited/Merged
    * Description: RealTek 875T-606 Clock Generator
    *
    * Author: nando4 - Darth_nVader -forums.notebookreview.com
    *
    * Modifed from ics94215.c-ics9lprs355.c
    * Author: Nikolay Kislitsa <deusexbeer@mail.ru>, (C) 2005
    *
    *
    */
    #include "smbus.h"
    #ifdef DEBUG
    #include <stdio.h>
    #endif
    
    typedef struct
    {
    	unsigned char fsb;
    	unsigned char ctrlb;
            unsigned char ctrlb1;
    } PLL_t;
    #define SMBUS_DEVICE 0x69
    #define BYTECOUNT    32
    #define CONTROLBYTE  0x11
    #define CONTROLBYTE1 0x13
    #define CMD 0x00
    
    static int FSBIndex = 0;
    
    static const PLL_t const pll[] =
    {
    /* Table containing three values
     * FSB, CONTROLBYTE, CONTROLBYTE1 
     * Gathered by setting FSB using setfsb, then reviewing the Diagnosis
     * screen to identify what data changed
     */
    	{ 100, 0x58, 0x23},
            //{ 117, 0x88, 0x87},
            //{ 125, 0x88, 0xA3},
    	{ 133, 0x20, 0x33},
      	//{ 142, 0x88, 0xDB},
            //{ 150, 0x88, 0xF7},
            //{ 158, 0x48, 0x13},
    	{ 167, 0xE8, 0x33},
    	{ 183, 0x4C, 0x43},
            { 200, 0xB0, 0x43},
    	{0}
    };
    /* If FSB=133, write original TME block data back to PLL */
    
    int ics9lprs355_SetFSB(int fsb)
    {
    /* default FSB=166.7Mhz table  
     * We need to change 0x00 bit 2 to 1 First(65), then SetFSB changes Bit 1 to 1(67),next we change Byte 0x01 to 0x89, 0x11 and 0x13 are the Clock Values for the FSB, Bytes 0x29 0x30 and 0x31 set some magic so we must change them too. We seem to Only need to write 32 Bytes of Data, the RTM875t-606 has 48 Byte Control Registers, but 0x33-0x48 seem to change
     Correct, so we don't try to deal with them at all.
     */
    
    	int i, res;
    	unsigned char buf[] = {0x67, 0x89, 0xFF, 0xFF, 0xFF, 0x00, 0x30, 0x1E,\
                                 0x10, 0x25, 0x7D, 0x00, 0x0D, 0x00, 0x00, 0x00,\
                                 0x50, 0xE8, 0x20, 0x33, 0x00, 0x00, 0xB6, 0x53,\
                                 0x5F, 0x00, 0x22, 0x00, 0x33, 0x32, 0x30, 0x57 };
    
    	if(fsb < 0) return -1;
    
    	for(i=0; pll[i].fsb; i++)
    		if(pll[i].fsb == fsb)
    		{
    			buf[CONTROLBYTE] = pll[i].ctrlb;
    			buf[CONTROLBYTE1] = pll[i].ctrlb1;
                            break;
    		}
    	if(!buf[CONTROLBYTE]) return -1; 
    
            res = smbus_write_block_data(SMBUS_DEVICE, CMD, BYTECOUNT, buf);
                  
    	if(res < 0) return res;
    #ifdef DEBUG
    	else printf("DEBUG: %i bytes written : ", BYTECOUNT);
    	for(i=0; i<BYTECOUNT; i++) printf("%02X ", buf[i]);
    	printf("\n");
    #endif /* DEBUG */
    	return 0;
    }
    
    int ics9lprs355_GetFSB()
    {
    	int i, res;
            /* Empty 32 byte buffer */
    	unsigned char buf[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 
                                   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 
                                   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
                                   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
    
            res = smbus_read_block_data(SMBUS_DEVICE, CMD, buf);
    
    	if(res < 0) return -1;
    #ifdef DEBUG
    	else printf("DEBUG: %i bytes read : ", res);
    	for(i=0; i<res; i++) printf("%02X ", buf[i]);
    	printf("\n");
    #endif /* DEBUG */
    
    	for(i=0; pll[i].fsb; i++)
    		if(pll[i].ctrlb == buf[CONTROLBYTE]) return pll[i].fsb;
    
    	return -1;
    }
    
    int ics9lprs355_CheckFSB(int fsb, float *sdram, float *pci, float *agp)
    {
    	int i;
    
    	if(sdram) *sdram = -1.0;
    	if(pci) *pci = -1.0;
    	if(agp) *agp = -1.0;
    
    	if(fsb < 0) return -1;
    
    	for(i=0; pll[i].fsb; i++)
    		if(pll[i].fsb == fsb) return 0;
    	return -1;
    }
    
    int ics9lprs355_GetFirstFSB()
    {
    	FSBIndex = 0;
      if(pll[FSBIndex].fsb) return pll[FSBIndex].fsb;
      else return -1;
    }
    
    int ics9lprs355_GetNextFSB()
    {
    	FSBIndex++;
    	if(pll[FSBIndex].fsb) return pll[FSBIndex].fsb;
    	else return -1;
    }
    View attachment rtm875t-606.txt

    If you look at some of the Code Comments, I explain some of the Magic Bits:

    0x00 the last/first half Byte will differ for those with 533/800Mhz FSB CPU's (6)<--is of course 667Mhz, and that's what I write to that address, however, as these Bits are RO, it should work for those with 533/800 FSB CPU's. The first/last half Byte should also be set to 7(Have a look at the ics9lprs355 DataSheet for what is done).

    0x01 is also Changed to 0x89(Have a look at the ics9lprs355 DataSheet for what is done).

    0x11 and 0x13 are the Registers that change the Clock Value of the FSB/DRAM

    0x1D, 0x1E, and 0x1F These need to be SetUP Before the Values of 0x11 and 0x13 are Valid/Read, I don't know why, but I don't need to, just write 32 30 57 and it's all good.

    I get lockup @100Mhz FSB with setfsb.mod, so 133 is the best safe(underclocked) FSB for me, I also see this in XP SetFSB, sometimes. However sometimes 100Mhz works just fine?

    I can't go past 203Mhz without lockup, I think my RAM is to blame, as it only have SDP Timing for 200/266/333 DDR, so if someone with a 800Mhz CPU and/or better RAM can help, we can ADD Values for 200+FSB, as it is now we don't know the Values for 0x11 and 0x13. 200Mhz.jpg :eek:
     
  4. Darth_nVader

    Darth_nVader Notebook Consultant

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    Also, I have to say, I impressed with Grub2 and Uncle Joe/Nando4's work with adding lfsb/i2c-dev/i801 code. One of many times, I'm happy to be wrong.

    One BootLoader to rule them all, One BootLoader to find them, One Bootloader to bring them all..........
     
  5. bigdr

    bigdr Notebook Enthusiast

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    The PLL chips has TME-locked, and it's still oc in grub2 bootloader?
     
  6. User Retired 2

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    grub2-setfsb just sends PLL config data to the PLL, which you obtain using Windows setfsb Diagnosis window.

    This means that if you can't get your PLL to OC in Windows using setfsb, you can't get OC using grub2-setfsb.
     
  7. KieserFiller

    KieserFiller Newbie

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    Hi everyone,
    I've bought intels new atom based board D510MO (specs here) and am trying to save some power by checking out the undervolting/underclocking capabilities of that baby.
    This thread is the only one i found on the internet where some guys seem to know how that could be done.
    First, his box is headless (I just don't have any display to connetct it to), is running a gentoo and will be running 24/7 as my nas/router/backup storage.
    Second, I've no experience in diggin into register directly, so please point me to some documentation if you know anything worth reading.

    I've read this thread, found the chip on my board, its a ICS 9LPRS525AGLF. Its datasheet is found here.

    thats its i2c dump:
    Code:
    #i2cdump 0 0x69
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    10: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    20: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    30: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    40: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    50: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    60: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    70: 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d 0d    ????????????????
    80: 61 d9 fe ff ff 00 00 01 03 25 83 26 0d d3 a5 13    a??....??%?&????
    90: 3c 83 1b ff 3e 65 88 87 00 04 cd 5e 01 bc 0f 00    <??.>e??.??^???.
    a0: 61 d9 fe ff ff 00 00 01 03 25 83 26 0d d3 a5 13    a??....??%?&????
    b0: 3c 83 1b ff 3e 65 88 87 00 04 cd 5e 01 bc 0f 00    <??.>e??.??^???.
    c0: 61 d9 fe ff ff 00 00 01 03 25 83 26 0d d3 a5 13    a??....??%?&????
    d0: 3c 83 1b ff 3e 65 88 87 00 04 cd 5e 01 bc 0f 00    <??.>e??.??^???.
    e0: 61 d9 fe ff ff 00 00 01 03 25 83 26 0d d3 a5 13    a??....??%?&????
    f0: 3c 83 1b ff 3e 65 88 87 00 04 cd 5e 01 bc 0f 00    <??.>e??.??^???.
    
    All interesting registers seem to start at 0x80, so any register mentioned in the datasheet is added to 0x80, right?

    I can see register 0x89 is at value 0x25, which is 0b00100101, its sixth bit is zero -> TME is off. Is that correct?

    The first three bits of register 9 are called "IO Output voltage select", is that the cpu voltage? default is 0.8V, i tried to set it lower, eg to 0.7V by executing
    Code:
    i2cset 0 0x69 0x89 0x24
    
    the chip seems to accept it, as i2cdump shows the new value, but power consumption of the systems stays the same. I went down to 0x20, which is 0.3V (i hoped the cpu would crash at that low voltage, but it did not), but still it makes no difference in that systems power usage.

    Did I miss something? done anything wrong? Will try to manipulate the FSB of the system tomorrow, hopefully that works out...
    Are there any bits I should take a look at to save some power?
    I imagine writing kind of a cpufreq governor which will check the systems load and clock it higher or lower on demand, setting appropriate voltages, but first I try to understand how that tricky register setting works and what can be done in order to save power vs computing speed and how reliabe this works.
    Any help, hints, links are appreciated.
     
  8. User Retired 2

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    Setting byte 9, bit 0-2 from "101" (0.8V) to "000" (0.3V) had no effect on my system's power consumption, nor did it crash the system. Not clear what that I/O voltage is.

    To control CPU voltage try phc (processor hardware control). Only problem I believe is that atoms don't have programmable VID to go along with FIDs. I haven't seen anyone report successfully undervolting an atom using rmclock either. If you did save some power it would be negligble in the scheme of things. An atom is already rated at 2.5W TDP. Your I/O chip uses more power.
     
  9. KieserFiller

    KieserFiller Newbie

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    Btw, the Atom D510 is rated at 13W TDP, its chipset 2W...

    Today I tried to manipulate FSB, but it didn't work out :/
    The specs tell bits 5,6,7 in byte 0 are the ones defining frequencies, but sadly they are read-only. I tried to change the values, but well, they are really read only ;)

    Their default value is "Latch", which means, as far as I get it, they allow to write exactly one value and then stay with that as long the system is running.

    Is there any way to open this latch and rewrite bits?

    I'm stumped at this point, is there anything left I can try to save power?
    Hmm, i'll try to disable a core now, maybe this works out, at least.
     
  10. User Retired 2

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    1. If the CPU is socketted, try a CPU pin voltmod as shown here. D510 datasheet has a VID table ranging from 0.7V to 1.2V.

    2. Modify core voltage regulator as shown here.

    3. Check if your PLL is TME-locked as shown here. Can pinmod it to unlock it so that PLL can be programmed using software. This would allow you to overclock up to whatever your CPU voltage allows. You may have some gains underclocking as well, moreso if can combine with (1) and (2) above.
     
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