Ryzen vs i7 (Mainstream); Threadripper vs i9 (HEDT); X299 vs X399; Xeon vs Epyc

Discussion in 'Hardware Components and Aftermarket Upgrades' started by ajc9988, Jun 7, 2017.

  1. ole!!!

    ole!!! Notebook Prophet

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    you gonna upgrade to zen2 TR when it comes out for 32 cores? or just 16 to 16c upgrade
     
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  2. jaybee83

    jaybee83 Biotech-Doc

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    depends on the performance stats id say. but from what is known thus far based on the zen 2 arch and 32 core epyc, the 32 core TR will likely be a BEAST to behold :) plus, going 16 core TR doesnt make much sense if u can just get the 3950x mainstream 16 core sku.
     
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  3. ajc9988

    ajc9988 Death by a thousand paper cuts

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    If the rumor on 8-channel memory for TR is true (there are two chipsets shown for TR on the USB filings, one labeled like TR40, the other as TR80, then a WR80 (which is likely Epyc)), then I may hold off until the 8-channel is available. It also might require a higher core count than 16-core (unless they used a similar idea to my ID pin where when in the right board, all 8-channels are activated, which would mean they might have all 8-channels on all chips, or just on a few chips, like 32 through 64 core variants). So it will depend.

    I also was thinking, with the cost of top binning seen on the 12-core, they may charge like $400-600 over price for the top bin from Silicon Lottery, which would mean it would be better for me to just buy a higher core count chip and roll the dice this time (even if I really don't need more cores but more mem bandwidth).

    Also, since Elmor turned over ZenStates to Github, one of the indie developers added the device ID to it for Epyc. So, if he can get all core OC working, I might consider going Epyc earlier than Zen 4, which was my planned switch, just for the I/O AND the mem channels. Unfortunately, mem OC on server platforms is locked down, so you are stuck at 3200MHz, but you can tighten timings and you still get a large bandwidth boost!

    I really don't get why lock down the server chips that much. Instead, let them boost to whatever the cooling can handle and get the server companies to beef up the VRM a bit (not crazy, but maybe get them to go from the 7 phases with 60A and 70A mosfets to doublers or a larger controller chip, giving a little more power headroom while spreading VRM heat over a larger area (more mosfets)). That way you have a bread and better, standard server boards that are for the masses, while having a couple boards that can really let it stretch its legs, especially as water cooling is starting to be incorporated more often into the racks.

    With that, let it run at the rated speeds, like they are doing, but allow them to flip a switch in the bios or control software so that it has a bias to boost similar to the desktop chips, giving free performance scaling beyond the rated. Many companies won't use it, but I think it would be nice for server workstations, etc.

    Doing that also would solve the issue of worrying about TR cannibalizing the Epyc chips. It basically is a win all around and can let OEMs create customized solutions on cooling and chassis to take advantage of it, while further crushing the Xeons on performance. By making it optional, all mission critical stick with rated performance (sometimes just base clock). Anyone else can choose to use that boost and truly scale the performance of those chips.
     
  4. ajc9988

    ajc9988 Death by a thousand paper cuts

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    I'll disagree. Quad channel mem and 64 lanes of PCIe helps if you want to do add-in cards. I've been considering building out a raid storage array with a raid 6 SAS/SATA card, since I already have a couple SAS/SATA enterprise 8TB drives and am going to be buying at least 2 more by next month.

    Unfortunately multi-GPU is dying and my work, at the moment, does not need multiple cards for scaling outside of gaming (although I wish more was being done for cryptographic cards, generally).

    But I wouldn't go to mainstream on the basis of dual channel mem alone (at least not until they put at least a 500GBps HBM interface on the CPU with at least 16GB of HBM2/3 on it).

    But that is a personal choice there.

    Here are my Sisoft Sandra cryptography scores (note the ranking)
    https://ranker.sisoftware.co.uk/top...f5c8f9dfb78abf99e1dceccaafcaf7cee89ba696&l=en
    https://ranker.sisoftware.co.uk/top...f2cfffd9b18cbc9ae2dfefc9acc9f4c4e291ac9c&l=en

    Edit: and yes, I do realize crypto can be done with GPUs, but...
     
  5. ole!!!

    ole!!! Notebook Prophet

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    forgot theres the 3950x still coming in september so hes right kinda pointless theres already a 16 cores. though extra pcie lanes and quad channel is nice to have.

    8 channels on 16 cores seems way overkill much more suited for 64 cores i'd say.
     
  6. ajc9988

    ajc9988 Death by a thousand paper cuts

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    If you don't need the bandwidth, it is overkill. If you do need the bandwidth, then it really isn't.

    Also, there are 8 and 16 core Epyc CPUs with 8-channel memory. But it only matters on workloads that need it and is, in part, about keeping the cache system fed. Think of bandwidth per core.
     
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  7. ole!!!

    ole!!! Notebook Prophet

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    theres no avx 512 i just dont see how u can use the bandwidth unless its very specified workload. on intel it would make sense for avx512 stuff
     
  8. ajc9988

    ajc9988 Death by a thousand paper cuts

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    That's a joke, right? Seriously, servers are CONSTANTLY bandwidth constrained on memory WITHOUT AVX512 workloads. AVX512 is a very NICHE use case in servers TO THIS DAY! That is actually why AMD said they will sit back and wait for Intel to get software to adopt it, then they will add the instruction set, but not before that. Pure and simple, they conceded that segment until there is more adoption.

    Moreover, back when people thought that the 2990WX was memory constrained, before everyone found out about the scheduler (which was part of the issue, see the latency chart in the Anandtech article for the Rome release), and ignoring for a moment my theory on stale data issues (which also relate to scheduler insofar as the scheduler does not contain higher quality latency awareness characteristics), they were examining, in articles like this one from PC World (https://www.pcworld.com/article/329...ng-amds-32-core-threadripper-performance.html) memory bandwidth relative to core count. Or how about this one from TechSpot (https://www.techspot.com/review/1678-amd-ryzen-threadripper-2990wx-2950x/page4.html).

    They were not wrong to suspect memory bandwidth can effect performance. It is a matter of whether or not the task the CPU is performing requires the memory bandwidth to keep the cache and cores fed. The more bandwidth, in theory, the better. What matters is that it can keep the cores fed with little down time. Then comes the latency portion (which is what we talked about at length prior, and which AMD needs to work on, but why they greatly enlarged the L3 cache to combat latency to the memory, even at the cost of higher latency when accessing the L3 cache, which the trade off there was obviously worth it).

    Edit: think of it as a pipe. You need water. If the pipe is too small, it takes a long time to fill your bucket, right? Think of bandwidth as widening that pipe. If you have a larger size pipe, you can get more water through it quicker. That is how it keeps the cores and cache fed.

    Now, then comes latency. You have a large pipe, so you can fill your buckets with ease. But, it still takes a certain amount of time to get that water into the bucket. You can shorten the distance of the pipe to the water source and that can reduce the time to fill the bucket. You can maybe change the material of the pipe to try to get the water to act differently, like reducing friction causing turbulence in the water. Or you can reduce the number of right angles, etc.

    In the same way, you have to work on both making sure the volume of data (your bandwidth) isn't constrained for your workload, but you also need to find ways to shorten the time for that data to get where it is going.

    Edit 2: Here is an examination that, a bit down, looks at memory bandwidth relative to workload tasks. https://externaltable.blogspot.com/2017/09/performance-analysis-of-cpu-intensive.html
     
    Last edited: Aug 23, 2019
  9. ole!!!

    ole!!! Notebook Prophet

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    did you not read what i said or you jumping into assumption and conclusion again? im asking you, not the server needs. i mean TR is HEDT so the enterprise would just go straight to eypc and skip HEDT.

    what do YOU have use for 8 channel, its way overkill for YOU unless you have something you can take advantage of.
     
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  10. ajc9988

    ajc9988 Death by a thousand paper cuts

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    I have hobbies, which include working with video encoding. In addition, I have plans to pick up the books I have on coding in the future, as some of the things I would like to do do not have software optimized in the way I want, etc.

    I resell some hardware, but I more often repurpose it (referring to personal hardware). As such, when it gets deprecated, it is either gifted or repurposed. My 1950X, for example, shall be repurposed into a media server with on the fly transcoding capabilities, among others.

    One of the things I plan to learn is creating an A.I. that can pick up logical fallacies in arguments and disconnects between statements. This is both to analyze my source material I am critiquing as well as alert me when I left out a detail necessary for my arguments, all without relying on other editors, etc.

    But what I use it for, or have planned for it, is my concerns. Just like separating memory for VMs is my concern, as we are finally getting closer and closer to me just using terminals and back powering everything with servers.

    So what is YOUR point? Other than trying to be a prick back for me calling you out on there being uses other than AVX512 and you now deflecting here?
     
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