PLL Pinmod Overclocking Methods and Examples

Discussion in 'Hardware Components and Aftermarket Upgrades' started by moral hazard, Jun 24, 2009.

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  1. moral hazard

    moral hazard Notebook Nobel Laureate

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    WARNING: The information on this thread is for educational purposes and following any instructions may void your warranty and also cause major damage to your notebook. If you don't know how to monitor system temperature and what the tjmax of your CPU is then please skip this.

    ---->NEW: SetPLL, free alternative to SetFSB<----

    How overclock a notebook with a TME-locked PLL or some other blockade

    Successful PLL pinmods using ideas from this post is summarized below

    OC details linkPLLPinmod type^1Normal SpeedOC Speed
    MSI GX740ICS9LPRS113AKLFFSLxi5-430M-2.26@1333.40@200
    Acer AS5740GSLGSP585FSLxi3-330M-2.13@1332.62@167
    Acer AS5740GICS9LPRS3197FSLxi3-330M-2.13@1332.62@167
    Gateway p7805uICS9LPRS365BGLFTME-unlockP8400-2.4@2663.61@400
    Dell Lat E4300 ^4SLG8LP554FSLxP9400-2.53@2663.16@333
    Quanta TW8 SLG8SP513VFSLxT4500-2.3@2003.06@266
    HP 6730PICS9LPRS397DKLFTME-unlockP8600-2.4@2663.06@333
    HP 8530W^3SLG8SP533VTME-unlockP8600-2.4@2663.06@333
    HP dv6-1000^4SLG8sp513vFSLxP8400-2.26@2.43.00@266
    Dell E5400^4SLG8LP554VFSLxT7300-2.2@2002.93@266
    HP 2530PICS9LPRS397DKLFTME-unlockSL9600-2.13@2662.90@323
    HP CQ45 & SLG8SP553VFSLxP8400-2.26@2662.82@333
    HP 2530PICS9LPRS397DKLFTME-unlock + FSLx^3SU9x00@200SU9x00@266Mhz+
    Alienware M11xR1ICS9LPRS387BKLFTME-unlockSU7300-1.6@2662.00@333
    Acer 1810TSLG8SP513VFSLx+BSEL & TME-unlockSU4100-1.3@2001.73@266
    Acer 1810T & & &ICS9LPRS365FSLx+BSEL & TME-unlockSU3500-1.4@2001.70@242
    Fujitsu Amilo Pi3560ICS9LPRS365BKLTME-unlock @200@233
    Santa Rosa
    Dell M1730*SLG8LP550 FSLxX9100-3.0@2004.0@266
    Clevo M570RU^5 &ICS9LPR365DGLFFSLxX9000-2.8@2003.74@266
    Dell XPS M1330 &SLG8LP550VFSLxT9300-2.5@2003.59@266
    Lenovo T61^3^4ICS954309FSLxT9300-2.7@2003.59@266
    ACER 6920g^3^5ICS9LPRS365BGLFTMEX9000-2.8@2003.5+
    HP HDX 9000 &ICS9LPRS501PGLFFSLx & TME-unlockT9300-2.5@2003.37@250
    Dell XPS M1730^3CY28547 FSLx200Mhz PLL266Mhz PLL
    HP Pavilion dv9700t RTM875T-606TME-unlockT9300-2.5@2003.13@250
    Lenovo T61SLG8LP564VFSLxT8300-2.4@2003.2@266
    Lenovo X61 ^4SLG8LP564FSLxT7300-2.0@2002.93@266
    Acer 6920^4ICS9LPRS365BGLFTME-unlockT8300-2.6@2003.0@233
    HP 8710P ICS9LPRS355 TME-unlockT8300-2.4@2002.92@243
    Acer EX5620z^4 ICS9LPRS502PGLFTME-unlockT7500-2.4@2002.88@240
    Quanta TW7 ICS9LPRS365BGLFFSLxT8100-2.1@2002.80@266
    Fujitsu U9200 ICS9LPRS365BGLFFSLxT8100-2.1@2002.80@266
    Toshiba Tecra A9ICS9LPR501SGLTME-unlockT7300-2.0@2002.72@272
    Dell XPS M1330SLG8LP550VFSLxT7300-2.0@2002.66@266
    Acer Aspire 8920g RTM875T-606TME-unlockT8300-2.4@2002.60@217
    Dell Inspiron 1525 &ICS9LPRS365BKLTME-unlockT7250-2.0@2002.50@250
    Dell D630 SLG8LP550FSLxT7100-1.8@2002.40@266
    HP G60 ICS9LPR355BKLTME-unlockT4200-2.0@2002.40@240
    Compal FL90 ICS9LPRS365BGLFTME-unlockT7100-1.8@2002.40@240
    HP Pavilion DV6871us &RTM875T-606TME-unlockT5600-1.83@1662.20@200
    HP Pavilion DV2000^3ICS954305EKLFFSLxT2050-1.6@1332.00@166
    Acer Aspire 5920g ICS9LPRS365BGLFTME-unlockT5250-1.5@1661.61@179
    HP 2510P &^2^4ICS9LPRS355BGLFFSLxU7600-1.33@1331.60@160
    HP 2510PICS9LPRS355BGLFFSLx+BSELU7600-1.2@1331.2@200
    HP 2710P^3 ICS9LPRS355BKLFSLx & TME-unlockU7600-1.2@1331.50@166
    ^1 FSLx or FSLx+BSEL mod means a large overclocking jump eg: 166/200/266/333/400 FSB. TME-unlocked PLLs means can use 0.3Mhz increments up to the point of instability via setfsb software overclocking.
    ^2 not necessary other than for convenience. Could have just used setfsb overclocking.
    ^3 theory requires implementation.
    ^4 running DualIDA capable bios and cpu gaining an extra half or full multiplier. Appears all recent Dell systems can do dualIDA.
    ^5 Throttlestop can unlock multipliers in the Core 2 Extreme CPUs making PLL overclock unnecessary.
    * is BSEL pinmodded from 266-]200 as described in

    This thread will help people extract peak performance from their notebook by showing:

    - how to check if your PLL is TME-locked, indicating setfsb OC won't work
    - method 1: TME-unlock a PLL via a pinmod so setfsb/grub2-setfsb can program the PLL
    - method 2 and 3: FSLx or FSLx+BSEL overclocking via PLL pinmod for a faster FSB.
    Before attempting any of these PLL overclock methods it might be worthwhile seeing if you can BSEL pinmod the CPU. Naton explains [click pic on right for visual understanding] The 200 -> 266 consists on connecting the two holes A23 and B23 on the CPU socket with a copper wire, or B23 and B24 with a copper wire. Though it will lock your multiplier to the lowest setting for all CPUs on Intel chipsets, except Celerons. AMD/NVidia chipsets allowing overclocking without multiplier lockout.[​IMG]
    1. Where can I get a schematic of my systemboard to identify my PLL and help if I need to pinmod? Try laptopdesktopschematic, lqv77, GSM-extreme, notebookschematic and a general google search.

    2. How do I check TME_READBACK to see if I can overclock my PLL with software?
    • using setfsb (Windows)
      Right: the status of TME_READBACK tells us if TME is enabled. Screenshot shows it's status on register 9 bit 6, shown as 65h=1100101(binary) bit 6=1, meaning no overclocking. In the next screenshot it is shown how to write a 0 to the PCI2 Output Enable register. If your system freezes after doing this then it uses the PCI2 signal for it's operation and it's not possible to pinmod the TME/PCI2 pin to remove the hardwired TME_Enabled mode, so continue to method 2. If the system works after the write, then refer to method 1 below.

      Both the ICS9LPRS355 and ICS9LPR501SGLF PLLs read TME_READBACK in this way, so it's highly likely other ICS PLLs do too.

    • using R-W Everything (Windows)
      1. Run r-w everything
      2. Select Access-Clock Generator
      3. Change byte 0C from 0D(13) to 16(22), click write close Clock Generator window
      4. Select Access->Clock Geneator. It will open same window as before but present 22bytes of data rather than 13.
    • using lmsensors (Linux)
      Setfsb's Diagnosis window requires a PLL to use for it's operation. Since newer PLLs aren't being added, we need an alternative way of checking the TME_READBACK flag using Linux.

      1. Install lmsensors package. Available for various Linux flavors on the repositories.

      2. Some distributions blacklist the i2c-dev or i2c-i801 module. Check your /etc/modules and uncomment if blacklisted

      3. Check that your bios has enabled the SMBUS device:
      $ lspci | grep -i smbus
      00:1f.3 SMBus: Intel Corporation 82801H (ICH8 Family) SMBus Controller (rev 03)
      If not, need to switch on the bits to enable it as explained here.

      4. Load i2c modules
      $ modprobe i2c-dev
      $ modprobe i2c-i801
      $ ls /dev/i2c*
      5. Scan to identify devices on i2c bus. ICS PLL appears as device 0x69

      $ i2cdetect -y 0
           0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
      00:          -- -- -- -- -- 08 -- -- -- 0c -- -- -- 
      10: -- -- -- -- -- -- -- -- -- -- -- -- -- 1d -- -- 
      20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
      30: 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
      40: -- -- -- -- 44 -- -- -- -- -- -- -- 4c -- -- -- 
      50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
      60: -- 61 -- -- 64 -- -- -- -- 69 -- -- -- -- -- -- 
      70: -- -- -- -- -- -- -- --
      6. Dump the PLL data

      $ i2cdump -y 0 0x69 s 0
           0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
      00: 31 85 fc 33 ff f0 90 11 d0 65 7d 00 0d             1??3.????e}.?
      $ i2cdump -y 0 0x69 s 0xd
           0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
      00: cf 44 ef 2f a0 8f f2 23 00 ce 61 53 d8             ?D?/???#.?aS?
      7. Check the TME_Readback flag to see if TME is enabled (no software overclocking)

      For ICS PLLs:
      - look at first dump, register 9, bit 6
      - if bit6=1 then it's TME-locked (no overclocking)

      For CYxxx PLLS
      - look at first dump, register 15, bit 7
      - If bit7=1 then it's TME-locked (no overclocking)
    3. Is there any software method to bypass TME mode without using a pinmod?
    setfsb's author Abo has successfully overcome the 2510P's ics9LPRS355 PLL TME mode via software configuration only. As far as I know this is the only PLL he has done this for. I was able to visually compare PLL registers before and after the overclock, referring to the ics9lprs355 datasheet to see what was done.

    We see that he swaps the main clock from PLL1 to PLL3, and the sata clock to PLL2 below. Can perform these steps or some variation of them to see if can overcome TME mode on the other PLLs are well.

    Right: 2510P PLL registers before/after setfsb applies TME workaround (OD, OE sets FSB)
    Step 1: set TME workaround
    1. 0h(0): 31->37
      Sets source for SRC Main from PLL1 -> PLL3
      Sets sata clock from SRC_Main to PLL2
    2. 11h(17): A0->A4
      VCO Frequency Control Register PLL3. M Div (5:0)
    3. 12h(18): 8F->F6
      VCO Frequency Control Register PLL3 N Div (9:0)
    4. 15h(21): 00->01
      M/N Enable
    Step 2: Set byte 0D and OE manually for your desired FSB
    { FSB, Byte 0D, Byte OE}
    { 112, 0x88, 0x71},
    { 117, 0x88, 0x87}
    { 125, 0x88, 0xA3}
    { 133, 0x88, 0xBF}
    { 142, 0x88, 0xDB}
    { 150, 0x88, 0xF7}
    { 158, 0x48, 0x13}
    { 167, 0x48, 0x2F}
    { 175, 0x48, 0x4B}
    { 183, 0x48, 0x67}
    { 190, 0x48, 0x7D}
    { 195, 0x48, 0x8E}
    { 200, 0x48, 0x9E}
    NOTE: one undersirable behaviour that the ics9lprs355 PLL shows is that when the system is put into standby/hibernate, it resumes in a state where the PLL won't respond to setfsb requests. It requires another quick standby to unfreeze it upon which it can respond to software overclocking requests.
    4. What methods can I use to overclock my PLL?
    • Intro
      The PLL's FSLx and the CPU's BSELx pins are tied. Method 2 is in effect a BSEL mod via the PLL's FSLx pins. Method 3 separates the PLL's FSLx signals and the CPU's BSEL signals to provide faster operation, a necessary workaround to prevent the CPU going into lowest multipler lockout when it's in an invalid (faster) BSEL setting.

      Software used for overclocking a PLL:
      • setfsb for Windows.
      • grub2 bootloader overclocking for OS-independent overclocking. Only provision is would need Linux, prefereably Ubuntu 9.10 or newer, installed to be able to compile and use it.

      PLL pins of interest: blue: method 1 | red: method 2/3. From ICS9LPR501SGLF PLL datasheet
    • RAM timing: how it affects overclocking potential
      Overclocking methods 1 and 3 below boot your system and set your northbridge, chipset and CPU internally to *believe* they will be receiving 200Mhz timings. They just are being sent faster signals from the PLL instead (266Mhz in method 3's case!!). This could present a problem with your RAM. DDR2-667 RAM will now be receiving timing signals for 266Mhz/887Mhz operation, yet still be using the SPD table for 667Mhz operation. In which case, I hope you've got good ram to test, or can use Thaiphoon Burner or SPDTool to slow down *at least* the CAS timing in your RAM's eeprom SPD table by increasing it's value. I believe it's CAS=6 for 800Mhz operation.

      For example if you have 800mhz DDR2 ram with an SPD like this:

      If you want to run it at 333mhz with a CAS of 6, open SPDtool, File > Read > Module X, then change "CAS Latencies Supported" from "4, 5, 6" to "6". Then just fix the checksum (under the Edit menu) and write the SPD. Make sure you save a copy of the original SPD in case you make a mistake.


      It's a good idea to try both thaiphoon burner and SPDtool, I don't think thaiphoon burner works well with 64-bit operating systems. And SPDtool may have problems with DDR3 ram. I have attached an older trial version of thaiphoon burner that has full functionality (does let you write the SPD). The latest trial version does not let you write the SPD, so I suggest using the latest trial version to modify the SPD and then use the old trial version to write the SPD. Unless you want to purchase thaiphoon burner.
    • Method 1: TME-unlock a PLL to allow software overclocking
      setfsb homepage informs us that a PLL ICS9LPR501HGLF is supported. So if the TME is disabled by setting PCI2/TME pin4 logic to 0 (GND), then setfsb can all software overclocking. Only problem here is *IF* your system uses the PCI2 signal after boot, in which case it won't work. I used setfsb setting ICS9LPRS355 PLL register 02, bit 2=0 to disable PCI2 output (enabled by default), and my system worked fine afterwards. This hardware TME-disabling hardware mod can be easily reversed:

      1. lift right side of the resistor leading from pin4 (blue) as shown in above picture using a soldering iron. Right side has more room and is easier if your right handed. Then can use the lifted resistor leg to attach a GND wire to. Try to minimise soldering iron contact with your multi-layered systemboard as much as is conveniently possible.

      2. Connect lifted resistor leg to a (logic 0) GND, found by continuity testing points against the system chassis.
      3. Put some insulation tape below the lifted resistor end so it won't short the board if pressed down.
      4. Test to see if it boots up. If not, reverse process and try method 2 or 3.
      • Example: TME-unlock applied to a Toshiba Tecra A9
        Configuration used

        - Toshiba Tectra A9. T7300 2Ghz CPU. PM965 Santa Rosa Chipset using FSB=800Mhz. DDR2-800 RAM.
        - In my particular case I had a TME on my PLL enabled, which was disallowing overclocking of the PLL.

        Requirements for overclocking

        - identify which PLL the notebook uses, then to download the datasheet for it.
        - Setfsb overclocking software. It's Diagnosis window useful to also read/write to the registers of the PLL.

        Problem with setfsb

        First problem was setfsb didn't have an exact match for my system's PLL ICS9LPR501SGLF PLL. So the closely matched ICS9LPR501HGLF was used instead. I press getfsb which does read the right frequency. Then I move the slider (top slider) a little bit and then press setfsb. The HDD lights up, I can move the mouse but not interact with anything. Then a few seconds later I get the BSOD and then the laptop restarts. This happens even if I don't move the slider, just press getfsb then setfsb. This also happens when I "Select source for SATA clock" to be "Sata = PLL2" That is, change bit 1 of byte 0 to 1. Which is what setfsb tries to change, among other things, but this is where it goes wrong. So the reasons setfsb didn't work for me are:

        1. My TME strap status (read only) reads 1 = no overclocking.
        2. System would lock up due to setfsb's ICS9LPR501HGLF overclock changing the SATA clock from PLL main to PLL2

        Hardware mod to disable TME mode

        I proceeded to use method 1 in Nando4's guide, requiring hardware modification to overcome the TME mode. The method being preferred to method 2 as

        - pin4 TME/PCI pin was easier to pinmod than pin57 FSLb pin
        - setfsb allows 1Mhz overclocking increments whereas method 2 is less probable 33/66Mhz overclocking

        This also required Abo to supply a new setfsb for my ICS9LPR501SGLF to correct the SATA clk issue.

        Here are photos of my PLL: before | after and after the modification.

        Basically as you can see from the photo I found that next to the resistor there was a GND pad and a pad that was connected to the TME pin (pin 4). I found this by using a multimeter. I tested points on the motherboard with the system chassis to find GND. I tested points on the motherboard with the pin 4 (TME pin) to find the second pad.

        So I removed the resistor and put it into the new position. I did some tests with a DMM to check my work and then closed the laptop back up. I started the laptop and it?s working perfectly, the best part is that now TME = 0, confirmed by reading the TME_READBACK register 9 bit 6 being 0.

        I used setfsb to increase the fsb a little, and I took a picture of my screen with a camera since setfsb causes my laptop to freeze. After the laptop restarted I then manually copied the register values that I saw in my camera to setfsb, except I did not change the source for the SATA clock. So bit 1 of byte 0 is 0. Then when I pressed apply it worked without freezing my notebook. Here is the screenshot.

        Overclocking after TME pinmod was applied

        I sent an email to Abo (creator of setfsb) and provided this info to him. He then gave me a test version that adding ICS9LPR501SGLF PLL support. The only difference now with setfsb between ICS9LPR501HGLF and ICS9LPR501SGLF is that the bit that is used to select the source for the SATA clock is unchanged in SGLF.

        Now using setfsb I was able to overclock my FSB to over 250mhz, my CPU frequency went from 2ghz to over 2.5ghz and is stable without and modifications to ram timings. This is lucky on my part. The RAM must be quite tolerant to run using the 333Mhz SPDTable timings and still work. It has been recommended that at the very least the primary RAM timing, CAS, be increased to ensure stability and allow me to overcome any RAM timing wall with overclocking. This would be done using spdtool or Thaiphoon Burner.

        Below are some screenshots of successful overclocking. Here is an album of successful OC screenshots.
        <!-- attachments -->
        <fieldset class='fieldset'>
        [​IMG][​IMG] [​IMG]
        <!-- / attachments -->
    • Method 2: FSLx mod to hardwire PLL for higher FSB
      Here we set different BSEL and FSLx signals as a workaround to prevent CPU being locked to the lowest multiplier. Here need to:

      1. separate the Pin57 FSLb pin from board so the CPU BSEL and PLL FSLx signals can be set separately
      2. set FSLb=0 by connecting to GND, eg: pin58.

      This would be most easiest if there is a resistor leading off the Pin57 track. What I can see is it looks as if it goes to a through hole, which disappears somewhere. If my observation is correct, you'd either need to follow that through hole and see if it leads to a resistor, or otherwise use a blade to disconnect the PLL's pin57 from the board and then connect it to pin58 (GND), putting some insulation tape below Pin57 so it doesn't make contact with it's original connected track, a logic of 1 (3.3V). Fiddly work.
    • Method 3: FSLx+BSEL mod to hardwire PLL for higher FSB
      Overriding PLL Frequency

      current operation, FSB=800Mhz
      desired overclock, FSB=1066Mhz
      red shows the PLL pin of interest

      From: ICS9LPR501SGLF PLL datasheet and Core2 Duo Processors for Mobile Intel 965 Express Chipset Family

      We can see the PLL's FSLC/FSLB/FSLA and the CPU's BSEL2/BSEL1/BSEL0 are tied. When the BSEL signals are sampled by the CPU and in a non-compatible range, it will lock the multiplier. So this will not work with recent CPUs using Intel chipsets, but will work with AMD/Nvidia CPUs.

      1. Flash the DDR2 RAM to PC2-6400 spec so has a 400Mhz SPDtable entry as described here.

      2. Applying a strong pull down resistor (2k to GND) to the PLL's FSLb pin to do a 200->266Mhz overclock. FSLb is pin 64 on the PLL as shown here).

      This overclock would be preferred since then the rest of the system would be calibrated correctly for this higher FSB, ie: RAM would use the 400Mhz SPDTable instead of the 333Mhz SPDtable, X4500's core and render clock speed would be adjusted by the chipset correctly.

      Once overclocked with these parameters, if the TME-unlock mod has been applied, the system may be even capable of going beyond the 266Mhz FSB by using setfsb. You may still need more voltage to the CPU for it to be stable. If can disable speedstep in the bios, then perhaps the CPU can be booted up in the lowest multiplier, stable long enough to then load rmclock to up the CPU voltages for the various dividers.

    1. What are the pros and cons of software versus hardware FSB overclocking?
    Obvious advantage of using setfsb is it gives overclocking ability in increments of 1Mhz, so it's far easier to find system limits than when dealing in 33/66Mhz increments if modding the PLL's FSLx signals using method 2 or 3 below. Though hardware overclocking presents these advantages:

    1. software overclocking using setfsb requires a rerun when come out of hibernate/standby
    2. Linux overclocking with setfsb requires a boot into Win, a setfsb run, then a warm boot into Linux.
    3. RAM timings still believe they are working at the lower FSB so the RAM SPD_table may need slower timings
    4. X3100 Core Render clock is FSB dependant, reflected by sampled BSEL signals as shown here.

    Hardwiring the PLL for faster FSB can overcome (1) and (2). If the chipset supports the higher FSB speed (eg: 533->800Mhz FSB overclock by Santa Rosa), then experimental method 3 above can overcome (3) and (4) whilst preventing multiplier lock-out. Though CPU would need to be very tolerant in such a higher overclock though.
    2. Can I also undervolt my CPU?
    Be sure to check The Undervolting Guide that can be found on this forum. Undervolting may be possible after an overclock but it will make the overclock less likely to be stable. There is a second guide Advanced Undervolting (using superlfm mode) with a slightly different approach.
    3. Are there any free alternatives to setfsb?
    NBR member Inteks has used the grub2-setfsb code to come up with a prelim setfsb successor in Windows. See setfsb code - Project Not working as yet but coders welcome to join the project to help it along.

    Inteks wrote 1810tray allowing overclocked-AC, undervolted-DC profiles but is now enhancing it for more generic notebook usage. setfsb being an important component.

    Would be very popular and could result in monetary gains:
    Money to the first guy who recreates a SetFSB alternative.(mobile i7 and C2D)
    4. Is it possible to use a 1066Mhz FSB Penryn cpu on a 800Mhz FSB Santa Rosa platform?
    NBR forum member naton has succeeded to get a T9900 (1066Mhz FSB) to run in a notebook with a GL960 chipset, after doing a BSEL mod to force the CPU to run with an 800Mhz FSB.
    Details are here.

    Related to this overclock, there are *some* hints that a 1066Mhz series-4 chipset penryn (1066Mhz FSB) cpu could work with a Santa Rosa systemboard. I've put together some info that may help you if you want to try a T9400/T9600 1066Mhz FSB CPU:

    1. Pin-compatibility between 1066Mhz and 800Mhz penryns

    Left: penryn CPU pinout for series 4 1066Mhz FSB chipsets
    Right: penryn CPU pinout for PM965/800Mhz FSB.

    We see they are directly pin compatible. Pics created by joining the two datasheet pinout pages together.
    [​IMG] [​IMG]
    2. BIOS compatible microcode

    If it won't boot, then consider whether new bios microcode is required to support the series-4 penryn CPU. There are tools for various bios and knowledgable on wimsbios->My CPU isn't recognised, mydigitallife and rebelshaven bios modding forums.

    There is a suggestion in the PM965 (800fsb) chipset and a 1066 MHz fsb cpu... thread:

    I called intel at 1-916-377-7000 I talked to Tom from Level 5 tech support he assured me that the intel 965m can support the new cpu however GATEWAY and only gateway can make that happen if they provide bios support for the qx9300 mobile quad cpu
    [QX9300 is a series-4 1066Mhz FSB quad-core CPU].

    3. Clocking the FSB at 1066Mhz on Santa Rosa platform

    If the T9400/T9600 boots up, then the mobo will downclock the CPU since the only valid BSEL settings a PM965 chipset has is 133/200Mhz. A PM45 has 200/266Mhz BSEL settings, so it would set it at 200Mhz FSB, BSEL2/1/0 being L/H/L. Can apply methods 0-3 above to increase from 800Mhz to 1066Mhz FSB on a Santa Rosa platform using setfsb and/or pinmods, or both if it's a TME-locked PLL.

    PM45 valid FSB

    PM965 valid FSB
    Left: 1066Mhz-spec FSB CPU's BSEL settings from Intel C2D 45-nm CPU datasheet. Compare this against the BSEL of 800Mhz-spec FSB CPU's BSEL settings as shown in method 2 above.
    Middle: 800Mhz-spec FSB CPU's BSEL pin as highlighted from Intel C2D CPU's based on 965 express familydatasheet
    Right: FSB capability comparison between the PM45 chipset that does support 1066Mhz FSB and the PM965 chipset that doesn't officially support 1066Mhz FSB (max=800Mhz). Anyone trying this mod is in a sense hopeful that the MCHBar functionality still exists if trying the PM45's BSEL selection on a PM965 system.

    The potential application here is two fold:

    1. to attempt to pinmod a 1066Mhz CPU to function on a Santa Rosa 800Mhz platform. A 1066Mhz CPU has a BSEL signal H/L/H - 200Mhz mode that is the the same as the Santa Rosa 800Mhz FSB platform. So if the CPU was installed, it should theoretically work, so long as the pinouts are compatible.

    The idea here being to set acceptable BSEL2/BSEL1/BSEL0 CPU signals so it doesn't apply multiplier locking, whilst sending a different set of BSEL signals to then rest of the system (CPU/PLL/Northbridge) to support a higher FSB operation. How to do this? CPU datasheet advises that BSEL2/1/0 are output pins so suggest:

    1. isolate the BSEL1 CPU pin from the circuit.
    2. run a logic 1 (3.3V) signal to BSEL1 . Test if this is necessary as it's supposedly an output pin.
    3. connect a 0 (GND) signal to PLL FSLb pin. Test if this is necessary as sometimes a disconnect is the same as a 0.

    Explanation: (2) makes the CPU believe its running in 200Mhz (800Mhz FSB) mode so it doesn't apply multiplier clamping. (1) then hardwiring the output of BSEL1 logic as seen by any other chips (eg: PLL, northbridge, GM965) to operate in PM45's 266Mhz mode (1066Mhz FSB).

    Precedents for success?

    PM965 (800fsb) chipset and a 1066 MHz fsb cpu... thread has comments
    kaltmond says: T9400 wont´t post in my PM965 nb, confirmed......

    Chaz, the moderators closes the thread with Yeah, this thread has reached the end of its usefulness . . read the previous posts. 1066MHz FSBs do not work in the mobile 965 chipset. End of story.

    1066 FSB CPU with 800MHz PM965 thread has RickAbraham tell us:
    I was talking with a bloke from a local PC repair shop and I watched him fit a T9600 processor into a Dell laptop running the PM965 Santa Rosa platform which is only 800MHz. The processor was fully compatiable which shocked me and I watched the machine boot up after the installation was complete. But what I want to know is are you going to get the full gain using a 1066 FSB when the chipset apparently doesnt support it. I have read on other forums that the PM965 refresh chipset is a freak some claim that it will support 8gb of ram and others claim 6gb of ram. Would the mobo downclock the CPU to 800 FSB or has anyone tested this upgrade and can prove that the chipset will run at 1066MHz ?? I am interested to find out.

    Pls report your results.

    Thanks go to nando4, for providing so much useful information and guidance as well as the NBR community for sharing their PLL pinmod experiences for others to benefit from.

    This guide is linked from Repair4Laptop: Do-It-Yourself Laptop & Notebook Upgrading, Modding, Repairing.

    Attached Files:

    Last edited by a moderator: May 12, 2015
  2. King of Interns

    King of Interns Simply a laptop enthusiast

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    I guess you have tried clockgen too?
  3. The_Moo™

    The_Moo™ Here we go again.....

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    ok i see the Chipset is not compatible ..sorry to intrude --post deleted
  4. catacylsm

    catacylsm Notebook Prophet

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    Describe when you say SETFSB does not work on your laptop, there are occasionally a few things you can do to make it work, but we need more details for now. :)

  5. Tinselworm

    Tinselworm Notebook Deity

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    that photo looks like a random shot of your motherboard, wheres the PLL chip?
  6. darnok44

    darnok44 Notebook Consultant

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    Actually probably Abo is right. If you will check in ICS9LPR501 datasheet description of pin number 4 you will read :"3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on
    power-up as follows
    0 = Overclocking of CPU and SRC Allowed
    1 = Overclocking of CPU and SRC NOT allowed
    After being sampled on power-up, this pin becomes a 3.3V PCI Output". That's probably SetFSB it's not working in your case, because on power up this input is set as 1 and it's probably done by a some kind hardware lock, blockade; Using reesistor in the circuit to force voltage to be set up on level which ist read as logical 1 for clock generator. And if this dont scary you we can move forward. That's the russian web page: where you find description with photos how to unlock for overclocking clock gen ICS9LPRS365 which if you look on it datasheet: have identical pinout like ics9lprs501. After this modification they ware able use setfsb for overclocking. That's probably what Abo refering to on his web site when he wrote about this ICS clock:"ICS9LPRS365BGLF (FS U9200 with the hardware remodeling".
    Ok. But after this mod they did next one; Bsel mod from 166 to 200Mhz of course on clock generator. That's what I was able undersand from this site, but lets just say that my russian it's far worst then my english and my english isn't very good too; besides google translator it's not helping too/.
    Ee Yaah I almost forgot and most important thing for You. I think that in your case changing from 200=266mhz it's just grounding FSLB pin 57 to neerest GND or connecting to FSA(10) or FSC(62). What i know signal "0" doesnt mean that on this pin thera no voltage at all it just mean that there're voltage on some certain lover level then on "1", but GND probably will work as well. And one more thing, that kind of mod was done by member of this forum :"Kaltmond" in his Clevo M570RU on clock generator ICS9LPR365DGLF, but like I said if you compare pinout of this two chips they are that same. You can find this thread here: I think he's the person with who you talk to.
    Ok that's everything what I Can help You. God bless russian overclockers, google translator and russian girls:D
  7. kaltmond

    kaltmond Clepple

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    If the mod is successful then your ram will run @ 887MHz, not 800.
  8. darnok44

    darnok44 Notebook Consultant

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    hi, I think that you mark wrong pins on the photo. This dot on the chip is probably for indicate pin number 1 if so your pin 57 and 58 will be on the other side of the chip( pin 7-gnd and pin 8-fsb from the top). That's what I thing

    Attached Files:

  9. moral hazard

    moral hazard Notebook Nobel Laureate

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    yes, you are right. I have made this mistake before.

    let me tell you the story:
    I wanted to do a simmilar modification on an older laptop but I was looking at the PLL upsidedown so I connected the wrong pins. I did this with solder and while I was trying to remove what I did, I damaged pins and it all wen't wrong. laptop never started again.

    So you have saved me this time, thankyou. I always assume that they print the info on the PLL the right way up, but it seems they do it upsidedown.

    again thankyou darnok44, +rep.
  10. kaltmond

    kaltmond Clepple

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    If you do this mod it´s a must to disconnect the PLL chip and MCH, and make sure CPU Socket unchanged, no direct BSEL wire pin mod, no isolate etc.

    @ moral, i have the service manual of my notebook, so i know where is the correct resistor to remove.
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