Thinkpad SATA 1.5GB/s limitation (with SSD)

[HUMAN2]

resurrection. my vertex is arriving next week and i would like to try this too

[HUMAN2]

great thread and hundreds of thousands may be intrested. i am very greatful on this find and on the post to upgrade, but does somebody have another explanation here or even a patch or modded driver perhaps?

[trieudoahong]

I'm think Txxx not have this limit, but not sure. The ultra bay on my T400 use SATA controller.

[Daniel L]

Here's what mine looks like. I'm not sure what to do next.

T61P running with x25m in AHCI mode.

[rbowen]

Hello all,

First post on this site, came here by way of magical Google I have a T61p. I have a OCZ Vertex in the mail, to be arriving next week. I spent about 6 hours researching this today (mostly learning how to read registers, do hexadecimal math, find offsets, use BAR-Edit, reading the ICH8 datasheet, etc).

So here's my findings:

My system was set on "Compatability" mode in the BIOS at first - I had to change this to AHCI mode to follow the directions. Make sure you check this BIOS setting!!!

The ABAR value on my thinkpad is FE226000. That's where you'll find the CAP registers, which is set to E710FF82 on my machine. I tried setting the CAP.ISS bits (23:20) to 2h and rebooting with BAR-Edit, however the CAP.ISS bits reverted to 1h after the reboot. Not sure what's going on here... I'll admit I'm a register hacking noob

For the PxCTL.SPD settings, my system was at 00000000 for all devices, which is (almost) the default for them. the 7:3 bit can be set to 0h (no speed limit), 1h (1.5GB/s) or 2h(3.0GB/s). Default is 0h.

The only thing I can think of what's going on here is the datasheet goes into mediocre detail about "Combined" mode - so even if you set your BIOS to "AHCI", I think it may automatically revert to Combined mode. Here's what strange about that however: The datasheet says that the MAP.MV and MAP.SMS values will be 01 and 00 respectively if the system is in combined mode - mine are set for what would be expected for full 3.0GB/s operation, MAP.MV = 00 (Non-combined) , MAP.SMS = 01 (AHCI Mode).

Interestingly though, the P0SSTS (Port 0 Serial ATA Status Register) says the link negotiated to the Generation 1 rate (1.5GB/s). I have a loaner drive one of the IT guys gave me (it's on it's last legs...) in the machine currently which very well may only support 1.5GB/s, so this is valid and expected.

Once my SSD arrives, I'll put some more elbow (knuckle?) grease into this and see where we end up.

Cheers,

Rick

[mullenbooger]

Awesome, good luck trying to crack this!

[miro_gt]

nice info. If works, would be priceless

[maumu]

folks does x200s have this bottleneck issue with SSD?

[rbowen]

Hi nando4,

I forgot to thank you for all your work you have put into this. So... THANK YOU!

I have a question though - CAP.ISS is R/WO (Read/Write Once). I'm trying to set the 23:00 hex value to 0010 (2h), however it automatically reverts to 0001 when i click 'Write'. I'm afraid perhaps the BIOS is setting this to 1h at boot time, using up the single write operation.

Any thoughts on this matter? If the BIOS is setting this bit at boot, are we out of luck without an official Lenovo BIOS fix?

[nando4]

Originally Posted by rbowen

Hi nando4,

I forgot to thank you for all your work you have put into this. So... THANK YOU!

I have a question though - CAP.ISS is R/WO (Read/Write Once). I'm trying to set the 23:00 hex value to 0010 (2h), however it automatically reverts to 0001 when i click 'Write'. I'm afraid perhaps the BIOS is setting this to 1h at boot time, using up the single write operation.

ABAR=FE226000h. CAP.ISS=ABAR+00h-03h (4 bytes). So check bits 23:20 at CAP.ISS=FE226000 and see if it's either 0001(1h - 1.5Gbs) or 0010 (2h - 3Gbps).

Given ABAR=FE226000, then CAP.ISS=FE22600+00h-03h (4 bytes). Since a bar edit write of 0001 (1h - 1.5Gbs) or 0010 (2h) at that address isn't being accepted then presumably Lenovo used up the single-write in bios to cap speed to 1.5Gbps. Q: How to get around that?


L: PLTRST# details referring to C9Fh reset control register
M: CF9h reset control register details
R: 0/31/0/Ach register also sets parameters for CF9h function

The datasheet against the Host Capabilities Register (CAP) tells us All bits in this register that are R/WO are reset only by PLTRST# . We see that PLTRST is controlled by the CF9h register, whose function can be somewhat set by the 0/31/0/ACh register . All of this is ideally done in bios, which sets up the SATA link, rather than a retrospective activity after bootup. So some suggestions then, perhaps applying them all in parallel?

1/ Continue by attempting a soft reset via CF9h, giving Write-Once access to CAP.ISS

2/ See if you can patch the bios file directly and then flash
Lenovo likely setting CAP.ISS=1h to cap the link speed to 1.5Gbps. You've identified the ABAR as FE226000 and looking at my previous notes this looks correct. Worth looking for FE226000 or reversed 006022FE in the raw bios file to see if they do a direct access to it mod the write from 1h to be a 2h. A bit advanced and Lenovo may have used offset addressing from a different base. Worth conversing with bios hackers at rebelhaven or mydigitallife forums if bios is not encrypted. Eg: HP encrypt their bios so it expands on runtime as an anti-tamper measure. Has Lenovo done the same?