M11x clock generator ICS9LPRS387BKLF

[HTWingNut]

I was trying to follow the posts, but I'm kinda lost here. So did someone actually OC their SU7300 over 3.0GHz? How?

[Thorpe24]

thats a different cpu, they are talking about getting up to 1.9 on th m11x.

[Mackan]

I was trying to follow the posts, but I'm kinda lost here. So did someone actually OC their SU7300 over 3.0GHz? How?

No, there are a couple of guys here with a Sager I think, which has the same PLL as the M11x. TME is disabled on that Sager, and they just figured out how to overclock their CPU via the PLL. Which is good news.

So to conclude, M11x still needs to be pinmodded to disable TME, and after that it should be possible to overclock the SU7300 I guess, preferably via SetFSB if the author of that program decides to support this PLL. Could maybe reach 1.9 GHz, as pointed out before. There is no way to increase voltage yet though. But if anyone has an idea for how to do that, would be interesting.

[HTWingNut]

Ok, thanks for clarification. If there's a pin mod though, forget it, I'm out. Already tried that on another machine and fubar'd it. 1.9GHz would be nice, but not enough IMHO for the hardware mod risk.

Now if they can boost the voltage, then definitely it might almost be worth it to pull it over 2GHz.

[Dufus]

Overclocking the 9LPRS387 PLL

First a thank you to rpg-XPS for the datasheet.

This is based on testing without full documentation and may contain errors.
Use at your own risk.
Do not use it for other types of PLL.
Corrections are welcome.


setFSB is used in this example but you could just as easily use clockgen.

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1.
Open setFSB
1. Select the Diagnosis tab.
2. Select the PLL diagnosis as the Clock Generator.
3. Press the "Get FSB" button and 13 bytes will be read in the "PLL Control Register"
4. Clicking on any of these bytes will load the byte into the Offset box for manipulation.

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2.
Click on byte 09h, if the box shown is a 1 instead of 0 then overclocking is disabled. For my own PLL it was a 1 but by removing a 10k pull up resistor connected to pin 14 of the PLL and +3V, it became 0. No resistor was required to pull the signal to ground.

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3.
Now we know there are more than 13 registers so where are they?. Well the byte count register 0Ch (12) is a read/write register. That means we can write in the number of bytes we want to read.
1. Click on byte 0Ch whose value is 0Dh (13) and change it to Hex 16h (which is 22 in decimal).
2. Click "Update"
3. Click "Apply".



We now have 22 registers showing (0-21).

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4.
Next we need to set some bits in register 0. There are 8 bits from 7:0. We need to make sure the Sata clock runs on PLL2 which is a fixed clock by making sure bit 1 is set to 1. For good measure we could also move the main SRC to PLL3 by setting bit 2 to 1. This would leave just our CPU clock on PLL 1.
Click on byte 0, modify as necessary and click "Update". It doesn't matter if you click "Apply" at this time or later.

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5.
Some bits in byte 0Ah (10) might need setting. By setting the bits 6:2 shown in the Bin box we will have enabled PLL3, enabled PLL2, disabled the SRC divider, disabled the PCI divider and enabled the CPU divider. In other words the only clocks we should be changing are that of the bus clock (CPU). Remember to use the "Update"

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6.
Now our bits are set we can enable the M/N divider by setting bit 0 of byte 15h (21). Again use "Update" and now use "Apply"

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7.
All that is left to do is start increasing our clock. The M/N divider for PLL1 resides in bytes 0Dh & 0Eh

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8.
Here we have increased N by 10h (16) from 68h to 78h using byte 0Eh (14). Each step of N in this case is equivalent to a ~2.54MHz change in bus clock. The result is the bus clock has increased by 16 x 2.54 = 40.6MHz from 266MHz to 307MHz. With a 9x CPU multiplier that results in a CPU frequency change from 9 x 266 = 2394MHz to 9 x 307 = 2763MHz. You may find your steps sizes are different depending on the original clock, ie 266 or 200 etc. and the default values of M and N.
Use "Update" & "Apply" to make the changes.

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Perhaps if this information were passed to Abo of setFSB with the datasheet he would be kind enough to included it in the PLL database, data permitting, thereby making the overclocking so much easier.

[DR650SE]

Dufus, +1 for the excellent write up. Do you know if this is compatible with the M11x? I don't have mine with me at the moment so I can't try it.

[MexicanSnake]

Excellent find Dufus!!! This hehehe higher m11x OC!!!

[jsgiv]

I checked the overclocking value on mine - it's set to a "1" - which indicates that the overclocking is disabled? (screenshot)

[HTWingNut]

@Dufus -

Whoa, dude, I'm not worthy

[Sirhcz0r]

@Dufus +rep.